Datasheet

Chapter 18 Periodic Interrupt Timer (S12PIT24B4CV2)
MC9S12XE-Family Reference Manual Rev. 1.25
680 Freescale Semiconductor
18.3.0.1 PIT Control and Force Load Micro Timer Register (PITCFLMT)
Read: Anytime
Write: Anytime; writes to the reserved bits have no effect
0x000F
PITCNT1 (Low)
R
PCNT7 PCNT6 PCNT5 PCNT4 PCNT3 PCNT2 PCNT1 PCNT0
W
0x0010
PITLD2 (High)
R
PLD15 PLD14 PLD13 PLD12 PLD11 PLD10 PLD9 PLD8
W
0x0011
PITLD2 (Low)
R
PLD7 PLD6 PLD5 PLD4 PLD3 PLD2 PLD1 PLD0
W
0x0012
PITCNT2 (High)
R
PCNT15 PCNT14 PCNT13 PCNT12 PCNT11 PCNT10 PCNT9 PCNT8
W
0x0013
PITCNT2 (Low)
R
PCNT7 PCNT6 PCNT5 PCNT4 PCNT3 PCNT2 PCNT1 PCNT0
W
0x0014
PITLD3 (High)
R
PLD15 PLD14 PLD13 PLD12 PLD11 PLD10 PLD9 PLD8
W
0x0015
PITLD3 (Low)
R
PLD7 PLD6 PLD5 PLD4 PLD3 PLD2 PLD1 PLD0
W
0x0016
PITCNT3 (High)
R
PCNT15 PCNT14 PCNT13 PCNT12 PCNT11 PCNT10 PCNT9 PCNT8
W
0x0017
PITCNT3 (Low)
R
PCNT7 PCNT6 PCNT5 PCNT4 PCNT3 PCNT2 PCNT1 PCNT0
W
0x0018−0x0027
RESERVED
R00000000
W
Module Base + 0x0000
76543210
R
PITE PITSWAI PITFRZ
00000
W
PFLMT1 PFLMT0
Reset 0 0 0 00000
= Unimplemented or Reserved
Figure 18-3. PIT Control and Force Load Micro Timer Register (PITCFLMT)
Register
Name
Bit 7 6 5 4 3 2 1 Bit 0
= Unimplemented or Reserved
Figure 18-2. PIT Register Summary (Sheet 2 of 2)