Datasheet

Chapter 18 Periodic Interrupt Timer (S12PIT24B4CV2)

MC9S12XE-Family Reference Manual Rev. 1.25

682 Freescale Semiconductor

18.3.0.3 PIT Channel Enable Register (PITCE)

Read: Anytime

Write: Anytime

Module Base + 0x0002

76543210

R0000

PCE3 PCE2 PCE1 PCE0

Reset 0 0 0 00000

Figure 18-5. PIT Channel Enable Register (PITCE)

Table 18-4. PITCE Field Descriptions

Field Description

3:0

PCE[3:0]

PIT Enable Bits for Timer Channel 3:0 — These bits enable the PIT channels 3-0. If PCE is cleared, the PIT

channel is disabled and the corresponding ﬂag bit in the PITTF register is cleared. When PCE is set, and if the

PIT module is enabled (PITE = 1) the 16-bit timer counter is loaded with the start count value and starts down-

counting.

0 The corresponding PIT channel is disabled.

1 The corresponding PIT channel is enabled.