Datasheet
Chapter 18 Periodic Interrupt Timer (S12PIT24B4CV2)
MC9S12XE-Family Reference Manual Rev. 1.25
686 Freescale Semiconductor
18.3.0.9 PIT Count Register 0 to 3 (PITCNT0–3)
Read: Anytime
Write: Has no meaning or effect
Table 18-9. PITLD0–3 Field Descriptions
Field Description
15:0
PLD[15:0]
PIT Load Bits 15:0 — These bits set the 16-bit modulus down-counter load value. Writing a new value into the
PITLD register must be a 16-bit access, to ensure data consistency. It will not restart the timer. When the timer
has counted down to zero the PTF time-out flag will be set and the register value will be loaded. The PFLT bits
in the PITFLT register can be used to immediately update the count register with the new value if an immediate
load is desired.
Module Base + 0x000A, 0x000B
15 14 13 12 11 10 9876543210
R
PCNT
15
PCNT
14
PCNT
13
PCNT
12
PCNT
11
PCNT
10
PCN
T9
PCN
T8
PCN
T7
PCN
T6
PCN
T5
PCN
T4
PCN
T3
PCN
T2
PCN
T1
PCN
T0
W
Reset 0000000000000000
Figure 18-15. PIT Count Register 0 (PITCNT0)
Module Base + 0x000E, 0x000F
15 14 13 12 11 10 9876543210
R
PCNT
15
PCNT
14
PCNT
13
PCNT
12
PCNT
11
PCNT
10
PCN
T9
PCN
T8
PCN
T7
PCN
T6
PCN
T5
PCN
T4
PCN
T3
PCN
T2
PCN
T1
PCN
T0
W
Reset 0000000000000000
Figure 18-16. PIT Count Register 1 (PITCNT1)
Module Base + 0x0012, 0x0013
15 14 13 12 11 10 9876543210
R
PCNT
15
PCNT
14
PCNT
13
PCNT
12
PCNT
11
PCNT
10
PCN
T9
PCN
T8
PCN
T7
PCN
T6
PCN
T5
PCN
T4
PCN
T3
PCN
T2
PCN
T1
PCN
T0
W
Reset 0000000000000000
Figure 18-17. PIT Count Register 2 (PITCNT2)
Module Base + 0x0016, 0x0017
15 14 13 12 11 10 9876543210
R
PCNT
15
PCNT
14
PCNT
13
PCNT
12
PCNT
11
PCNT
10
PCN
T9
PCN
T8
PCN
T7
PCN
T6
PCN
T5
PCN
T4
PCN
T3
PCN
T2
PCN
T1
PCN
T0
W
Reset 0000000000000000
Figure 18-18. PIT Count Register 3 (PITCNT3)