Datasheet

Chapter 20 Serial Communication Interface (S12SCIV5)
MC9S12XE-Family Reference Manual Rev. 1.25
Freescale Semiconductor 727
20.3.2 Register Descriptions
This section consists of register descriptions in address order. Each description includes a standard register
diagram with an associated figure number. Writes to a reserved register locations do not have any effect
and reads of these locations return a zero. Details of register bit and field function follow the register
diagrams, in bit order.
Register
Name
Bit 7 6 5 4 3 2 1 Bit 0
0x0000
SCIBDH
1
R
IREN TNP1 TNP0 SBR12 SBR11 SBR10 SBR9 SBR8
W
0x0001
SCIBDL
1
R
SBR7 SBR6 SBR5 SBR4 SBR3 SBR2 SBR1 SBR0
W
0x0002
SCICR1
1
R
LOOPS SCISWAI RSRC M WAKE ILT PE PT
W
0x0000
SCIASR1
2
R
RXEDGIF
0000
BERRV BERRIF BKDIF
W
0x0001
SCIACR1
2
R
RXEDGIE
00000
BERRIE BKDIE
W
0x0002
SCIACR2
2
R00000
BERRM1 BERRM0 BKDFE
W
0x0003
SCICR2
R
TIE TCIE RIE ILIE TE RE RWU SBK
W
0x0004
SCISR1
R TDRE TC RDRF IDLE OR NF FE PF
W
0x0005
SCISR2
R
AMAP
00
TXPOL RXPOL BRK13 TXDIR
RAF
W
0x0006
SCIDRH
RR8
T8
000000
W
0x0007
SCIDRL
RR7R6R5R4R3R2R1R0
WT7T6T5T4T3T2T1T0
1.These registers are accessible if the AMAP bit in the SCISR2 register is set to zero.
2,These registers are accessible if the AMAP bit in the SCISR2 register is set to one.
= Unimplemented or Reserved
Figure 20-2. SCI Register Summary