Datasheet

Chapter 20 Serial Communication Interface (S12SCIV5)
MC9S12XE-Family Reference Manual Rev. 1.25
Freescale Semiconductor 733
20.3.2.5 SCI Alternative Control Register 2 (SCIACR2)
Read: Anytime, if AMAP = 1
Write: Anytime, if AMAP = 1
Module Base + 0x0002
76543210
R00000
BERRM1 BERRM0 BKDFE
W
Reset 0 0 0 00000
= Unimplemented or Reserved
Figure 20-8. SCI Alternative Control Register 2 (SCIACR2)
Table 20-8. SCIACR2 Field Descriptions
Field Description
2:1
BERRM[1:0]
Bit Error Mode — Those two bits determines the functionality of the bit error detect feature. See Table 20-9.
0
BKDFE
Break Detect Feature Enable — BKDFE enables the break detect circuitry.
0 Break detect circuit disabled
1 Break detect circuit enabled
Table 20-9. Bit Error Mode Coding
BERRM1 BERRM0 Function
0 0 Bit error detect circuit is disabled
0 1 Receive input sampling occurs during the 9th time tick of a transmitted bit
(refer to Figure 20-19)
1 0 Receive input sampling occurs during the 13th time tick of a transmitted bit
(refer to Figure 20-19)
1 1 Reserved