Datasheet

Chapter 21 Serial Peripheral Interface (S12SPIV5)
MC9S12XE-Family Reference Manual Rev. 1.25
766 Freescale Semiconductor
21.3.2.2 SPI Control Register 2 (SPICR2)
Read: Anytime
Write: Anytime; writes to the reserved bits have no effect
1
SSOE
Slave Select Output Enable — The SS output feature is enabled only in master mode, if MODFEN is set, by
asserting the SSOE as shown in Table 21-3. In master mode, a change of this bit will abort a transmission in
progress and force the SPI system into idle state.
0
LSBFE
LSB-First Enable — This bit does not affect the position of the MSB and LSB in the data register. Reads and
writes of the data register always have the MSB in the highest bit position. In master mode, a change of this bit
will abort a transmission in progress and force the SPI system into idle state.
0 Data is transferred most significant bit first.
1 Data is transferred least significant bit first.
Table 21-3. SS Input / Output Selection
MODFEN SSOE Master Mode Slave Mode
00
SS not used by SPI SS input
01
SS not used by SPI SS input
10
SS input with MODF feature SS input
11
SS is slave select output SS input
Module Base +0x0001
76543210
R0
XFRW
0
MODFEN BIDIROE
0
SPISWAI SPC0
W
Reset 0 0 0 00000
= Unimplemented or Reserved
Figure 21-4. SPI Control Register 2 (SPICR2)
Table 21-2. SPICR1 Field Descriptions (continued)
Field Description