Datasheet

Chapter 22 Timer Module (TIM16B8CV2) Block Description
MC9S12XE-Family Reference Manual Rev. 1.25
Freescale Semiconductor 801
Read: Anytime
Write: Anytime.
22.3.2.10 Timer Interrupt Enable Register (TIE)
Read: Anytime
Write: Anytime.
Table 22-11. TCTL3/TCTL4 Field Descriptions
Field Description
7:0
EDGnB
EDGnA
Input Capture Edge Control — These eight pairs of control bits configure the input capture edge detector
circuits.
Table 22-12. Edge Detector Circuit Configuration
EDGnB EDGnA Configuration
0 0 Capture disabled
0 1 Capture on rising edges only
1 0 Capture on falling edges only
1 1 Capture on any edge (rising or falling)
Module Base + 0x000C
76543210
R
C7I C6I C5I C4I C3I C2I C1I C0I
W
Reset 00000000
Figure 22-18. Timer Interrupt Enable Register (TIE)
Table 22-13. TIE Field Descriptions
Field Description
7:0
C7I:C0I
Input Capture/Output Compare “x” Interrupt Enable — The bits in TIE correspond bit-for-bit with the bits in
the TFLG1 status register. If cleared, the corresponding flag is disabled from causing a hardware interrupt. If set,
the corresponding flag is enabled to cause a interrupt.