Datasheet

Chapter 22 Timer Module (TIM16B8CV2) Block Description
MC9S12XE-Family Reference Manual Rev. 1.25
Freescale Semiconductor 803
NOTE
The newly selected prescale factor will not take effect until the next
synchronized edge where all prescale counter stages equal zero.
22.3.2.12 Main Timer Interrupt Flag 1 (TFLG1)
Read: Anytime
Write: Used in the clearing mechanism (set bits cause corresponding bits to be cleared). Writing a zero
will not affect current status of the bit.
22.3.2.13 Main Timer Interrupt Flag 2 (TFLG2)
TFLG2 indicates when interrupt conditions have occurred. To clear a bit in the flag register, write the bit
to one while TEN bit of TSCR1 or PAEN bit of PACTL is set to one.
Read: Anytime
Write: Used in clearing mechanism (set bits cause corresponding bits to be cleared).
Any access to TCNT will clear TFLG2 register if the TFFCA bit in TSCR register is set.
Module Base + 0x000E
76543210
R
C7F C6F C5F C4F C3F C2F C1F C0F
W
Reset 00000000
Figure 22-20. Main Timer Interrupt Flag 1 (TFLG1)
Table 22-16. TRLG1 Field Descriptions
Field Description
7:0
C[7:0]F
Input Capture/Output Compare Channel “x” Flag — These flags are set when an input capture or output
compare event occurs. Clearing requires writing a one to the corresponding flag bit while TEN or PAEN is set to
one.
When TFFCA bit in TSCR register is set, a read from an input capture or a write into an output compare channel
(0x0010–0x001F) will cause the corresponding channel flag CxF to be cleared.
Module Base + 0x000F
76543210
R
TOF
0000000
W
Reset 00000000
Unimplemented or Reserved
Figure 22-21. Main Timer Interrupt Flag 2 (TFLG2)