Datasheet

Chapter 23 Voltage Regulator (S12VREGL3V3V1)
MC9S12XE-Family Reference Manual Rev. 1.25
820 Freescale Semiconductor
23.3.1 Module Memory Map
A summary of the registers associated with the VREG_3V3 sub-block is shown in Figure 23-2. Detailed
descriptions of the registers and bits are given in the subsections that follow
23.3.2 Register Descriptions
This section describes all the VREG_3V3 registers and their individual bits.
23.3.2.1 High Temperature Control Register (VREGHTCL)
The VREGHTCL register allows to configure the VREG temperature sense features.
Figure 23-2. Register Summary
Address Name Bit 7 6 54321Bit 0
0x02F0 VREGHTCL
R0 0
VSEL VAE HTEN
HTDS
HTIE HTIF
W
0x02F1 VREGCTRL
R00000LVDS
LVIE LVIF
W
0x02F2
VREGAPIC
L
R
APICLK
00
APIFES APIEA APIFE APIE APIF
W
0x02F3
VREGAPIT
R
R
APITR5 APITR4 APITR3 APITR2 APITR1 APITR0
00
W
0x02F4
VREGAPIR
H
R
APIR15 APIR14 APIR13 APIR12 APIR11 APIR10 APIR9 APIR8
W
0x02F5
VREGAPIR
L
R
APIR7 APIR6 APIR5 APIR4 APIR3 APIR2 APIR1 APIR0
W
0x02F6
Reserved
06
R00000000
W
0x02F7 VREGHTTR
R
HTOEN
000
HTTR3 HTTR2 HTTR1 HTTR0
W
0x02F0
76543210
R0 0
VSEL VAE HTEN
HTDS
HTIE HTIF
W
Reset 0 0 0 10000
= Unimplemented or Reserved