Datasheet

Chapter 23 Voltage Regulator (S12VREGL3V3V1)
MC9S12XE-Family Reference Manual Rev. 1.25
822 Freescale Semiconductor
23.3.2.3 Autonomous Periodical Interrupt Control Register (VREGAPICL)
The VREGAPICL register allows the configuration of the VREG_3V3 autonomous periodical interrupt
features.
Table 23-4. VREGCTRL Field Descriptions
Field Description
2
LVDS
Low-Voltage Detect Status Bit — This read-only status bit reflects the input voltage. Writes have no effect.
0 Input voltage V
DDA
is above level V
LVID
or RPM or shutdown mode.
1 Input voltage V
DDA
is below level V
LVIA
and FPM.
1
LVIE
Low-Voltage Interrupt Enable Bit
0 Interrupt request is disabled.
1 Interrupt will be requested whenever LVIF is set.
0
LVIF
Low-Voltage Interrupt Flag — LVIF is set to 1 when LVDS status bit changes. This flag can only be cleared by
writing a 1. Writing a 0 has no effect. If enabled (LVIE = 1), LVIF causes an interrupt request.
0 No change in LVDS bit.
1 LVDS bit has changed.
Note: On entering the Reduced Power Mode the LVIF is not cleared by the VREG_3V3.
0x02F2
76543210
R
APICLK
00
APIES APIEA APIFE APIE APIF
W
Reset 0 0 0 00000
= Unimplemented or Reserved
Figure 23-4. Autonomous Periodical Interrupt Control Register (VREGAPICL)
Table 23-5. VREGAPICL Field Descriptions
Field Description
7
APICLK
Autonomous Periodical Interrupt Clock Select Bit — Selects the clock source for the API. Writable only if
APIFE = 0; APICLK cannot be changed if APIFE is set by the same write operation.
0 Autonomous periodical interrupt clock used as source.
1 Bus clock used as source.
4
APIES
Autonomous Periodical Interrupt External Select Bit — Selects the waveform at the external pin.If set, at the
external pin a clock is visible with 2 times the selected API Period (Table 23-9). If not set, at the external pin will
be a high pulse at the end of every selected period with the size of half of the min period (Table 23-9). See device
level specification for connectivity.
0 At the external periodic high pulses are visible, if APIEA and APIFE is set.
1 At the external pin a clock is visible, if APIEA and APIFE is set.
3
APIEA
Autonomous Periodical Interrupt External Access Enable Bit — If set, the waveform selected by bit APIES
can be accessed externally. See device level specification for connectivity.
0 Waveform selected by APIES can not be accessed externally.
1 Waveform selected by APIES can be accessed externally, if APIFE is set.
2
APIFE
Autonomous Periodical Interrupt Feature Enable Bit — Enables the API feature and starts the API timer
when set.
0 Autonomous periodical interrupt is disabled.
1 Autonomous periodical interrupt is enabled and timer starts running.