Datasheet

Chapter 2 Port Integration Module (S12XEPIMV1)
MC9S12XE-Family Reference Manual Rev. 1.25
Freescale Semiconductor 91
Table 2-2 shows all the pins and their functions that are controlled by the Port Integration Module. Refer
to the SOC Guide for the availability of the individual pins in the different package options.
NOTE
If there is more than one function associated with a pin, the priority is
indicated by the position in the table from top (highest priority) to bottom
(lowest priority).
Table 2-2. Pin Functions and Priorities
Port Pin Name
Pin Function
& Priority
(1)
I/O Description
Pin Function
after Reset
- BKGD MODC
(2)
I MODC input during RESET BKGD
BKGD I/O S12X_BDM communication pin
A PA[7:0] ADDR[15:8]
mux
IVD[15:8]
(3)
O High-order external bus address output
(multiplexed with IVIS data)
Mode
dependent
(4)
GPIO I/O General-purpose I/O
B PB[7:1] ADDR[7:1]
mux
IVD[7:1]
3
O Low-order external bus address output
(multiplexed with IVIS data)
Mode
dependent
4
GPIO I/O General-purpose I/O
PB[0] ADDR[0]
mux
IVD0
3
O Low-order external bus address output
(multiplexed with IVIS data)
UDS O Upper data strobe
GPIO I/O General-purpose I/O
C PC[7:0] DATA[15:8] I/O High-order bidirectional data input/output
Configurable for reduced input threshold
Mode
dependent
4
GPIO I/O General-purpose I/O
D PD[7:0] DATA[7:0] I/O Low-order bidirectional data input/output
Configurable for reduced input threshold
Mode
dependent
4
GPIO I/O General-purpose I/O