Datasheet

Chapter 2 Port Integration Module (S12XEPIMV1)
MC9S12XE-Family Reference Manual Rev. 1.25
Freescale Semiconductor 119
2.3.17 IRQ Control Register (IRQCR)
2.3.18 PIM Reserved Register
This register is reserved for factory testing of the PIM module and is not available in normal operation.
Address 0x001E Access: User read/write
(1)
1. Read: See individual bit descriptions below.
Write: See individual bit descriptions below.
76543210
R
IRQE IRQEN
000000
W
Reset 01000000
= Unimplemented or Reserved
Figure 2-15. IRQ Control Register (IRQCR)
Table 2-17. IRQCR Register Field Descriptions
Field Description
7
IRQE
IRQ select edge sensitive only—
Special modes: Read or write anytime.
Normal & emulation modes: Read anytime, write once.
1
IRQ configured to respond only to falling edges. Falling edges on the IRQ pin will be detected anytime IRQE = 1
and will be cleared only upon a reset or the servicing of the
IRQ interrupt.
0
IRQ configured for low level recognition.
6
IRQEN
External IRQ enable—
Read or write anytime.
1 External IRQ pin is connected to interrupt logic.
0 External IRQ pin is disconnected from interrupt logic.
5-0 Reserved—
Address 0x001F Access: User read
(1)
1. Read: Always reads 0x00
Write: Unimplemented
NOTE
Writing to this register when in special modes can alter the pin functionality.
76543210
R00000000
W
Reset 00000000
= Unimplemented or Reserved
Figure 2-16. PIM Reserved Register