Datasheet

Chapter 2 Port Integration Module (S12XEPIMV1)
MC9S12XE-Family Reference Manual Rev. 1.25
120 Freescale Semiconductor
2.3.19 Port K Data Register (PORTK)
2.3.20 Port K Data Direction Register (DDRK)
Address 0x0032 (PRR) Access: User read/write
(1)
1. Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other modes the data source
is depending on the data direction value.
Write: Anytime. In emulation modes, write operations will also be directed to the external bus.
76543210
R
PK7 PK6 PK5 PK4 PK3 PK2 PK1 PK0
W
Altern.
Function
ROMCTL
or
EWAIT
ADDR22
mux
ACC2
ADDR21
mux
ACC1
ADDR20
mux
ACC0
ADDR19
mux
IQSTAT3
ADDR18
mux
IQSTAT2
ADDR17
mux
IQSTAT1
ADDR16
mux
IQSTAT0
Reset 00000000
Figure 2-17. Port K Data Register (PORTK)
Table 2-18. PORTK Register Field Descriptions
Field Description
7-0
PK
Port K general purpose input/output data—Data Register
Port K pins 7 through 0 are associated with external bus control signals and internal memory expansion emulation
pins. These include ADDR[22:16], Access Source (ACC[2:0]), External Wait (
EWAIT) and instruction pipe signals
IQSTAT[3:0]. Bits 6-0 carry the external addresses in all expanded modes. In emulation modes the address is
multiplexed with the alternate functions ACC and IQSTAT on the respective pins.
When not used with the alternative function, these pins can be used as general purpose I/O.
If the associated data direction bits of these pins are set to 1, a read returns the value of the port register, otherwise
the buffered pin input state is read.
Address 0x0033 (PRR) Access: User read/write
(1)
1. Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other modes the data source
is depending on the data direction value.
Write: Anytime. In emulation modes, write operations will also be directed to the external bus.
76543210
R
DDRK7 DDRK6 DDRK5 DDRK4 DDRK3 DDRK2 DDRK1 DDRK0
W
Reset 00000000
Figure 2-18. Port K Data Direction Register (DDRK)