Datasheet
Appendix A Electrical Characteristics
MC9S12XE-Family Reference Manual Rev. 1.25
Freescale Semiconductor 1239
A.6.3 Phase Locked Loop
A.6.3.1 Jitter Information
With each transition of the clock f
cmp
, the deviation from the reference clock f
ref
is measured and input
voltage to the VCO is adjusted accordingly.The adjustment is done continuously with no abrupt changes
in the clock output frequency. Noise, voltage, temperature and other factors cause slight variations in the
control loop resulting in a clock jitter. This jitter affects the real minimum and maximum clock periods as
illustrated in Figure A-5.
Figure A-5. Jitter Deļ¬nitions
The relative deviation of t
nom
is at its maximum for one clock period, and decreases towards zero for larger
number of clock periods (N).
2 3 N-1 N1
0
t
nom
t
max1
t
min1
t
maxN
t
minN