Datasheet

Appendix E Detailed Register Address Map
MC9S12XE-Family Reference Manual Rev. 1.25
1274 Freescale Semiconductor
0x0030–0x0031 Reserved Register Space
0x0030 Reserved
R00000000
W
0x0031 Reserved
R00000000
W
0x0032–0x0033 Port Integration Module (PIM) Map 4 of 6
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0x0032 PORTK
R
PK7 PK6 PK5 PK4 PK3 PK2 PK1 PK0
W
0x0033 DDRK
R
DDRK7 DDRK6 DDRK5 DDRK4 DDRK3 DDRK2 DDRK1 DDRK0
W
0x0034–0x003F Clock and Reset Generator (CRG) Map
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0x0034 SYNR
R
VCOFRQ[1:0]
SYNDIV5 SYNDIV4 SYNDIV3 SYNDIV2 SYNDIV1 SYNDIV0
W
0x0035 REFDV
R
REFFRQ[1:0]
REFDIV5 REFDIV4 REFDIV3 REFDIV2 REFDIV1 REFDIV0
W
0x0036 POSTDIV
R
000
POSTDIV[4:0]]
W
0x0037 CRGFLG
R
RTIF PORF LVRF LOCKIF
LOCK
ILAF SCMIF
SCM
W
0x0038 CRGINT
R
RTIE
00
LOCKIE
00
SCMIE
0
W
0x0039 CLKSEL
R
PLLSEL PSTP
XCLKS 0
PLLWAI
0
RTIWAI COPWAI
W
0x003A PLLCTL
R
CME PLLON
FM1 FM0
FSTWKP PRE PCE SCME
W
0x003B RTICTL
R
RTDEC RTR6 RTR5 RTR4 RTR3 RTR2 RTR1 RTR0
W
0x003C COPCTL
R
WCOP RSBCK
000
CR2 CR1 CR0
W
WRTMASK
0x003D FORBYP
R00000000
W Reserved For Factory Test
0x003E CTCTL
R0000 000
W Reserved For Factory Test
0x003F ARMCOP
R00000000
W Bit 7 6 54321Bit 0