Datasheet

Chapter 2 Port Integration Module (S12XEPIMV1)
MC9S12XE-Family Reference Manual Rev. 1.25
154 Freescale Semiconductor
2.3.67 Port J Interrupt Enable Register (PIEJ)
Read: Anytime.
2.3.68 Port J Interrupt Flag Register (PIFJ)
Address 0x026E Access: User read/write
(1)
1. Read: Anytime.
Write: Anytime.
76543210
R
PIEJ7 PIEJ6 PIEJ5 PIEJ4 PIEJ3 PIEJ2 PIEJ1 PIEJ0
W
Reset 00000000
Figure 2-65. Port J Interrupt Enable Register (PIEJ)
Table 2-63. PPSP Register Field Descriptions
Field Description
7-0
PIEJ
Port J interrupt enable—
This register disables or enables on a per-pin basis the edge sensitive external interrupt associated with Port J.
1 Interrupt is enabled.
0 Interrupt is disabled (interrupt flag masked).
Address 0x026F Access: User read/write
(1)
1. Read: Anytime.
Write: Anytime.
76543210
R
PIFJ7 PIFJ6 PIFJ5 PIFJ4 PIFJ3 PIFJ2 PIFJ1 PIFJ0
W
Reset 00000000
Figure 2-66. Port J Interrupt Flag Register (PIFJ)
Table 2-64. PPSP Register Field Descriptions
Field Description
7-0
PIFJ
Port J interrupt flag—
Each flag is set by an active edge on the associated input pin. This could be a rising or a falling edge based on the
state of the PPSJ register. To clear this flag, write logic level 1 to the corresponding bit in the PIFJ register. Writing
a 0 has no effect.
1 Active edge on the associated bit has occurred (an interrupt will occur if the associated enable bit is set).
0 No active edge pending.