Datasheet

Chapter 2 Port Integration Module (S12XEPIMV1)
MC9S12XE-Family Reference Manual Rev. 1.25
156 Freescale Semiconductor
2.3.71 Port AD0 Data Direction Register 0 (DDR0AD0)
NOTE
Due to internal synchronization circuits, it can take up to 2 bus clock cycles
until the correct value is read on PT0AD0 registers, when changing the
DDR0AD0 register.
NOTE
To use the digital input function on Port AD0 the ATD Digital Input Enable
Register (ATD0DIEN1) has to be set to logic level “1”.
2.3.72 Port AD0 Data Direction Register 1 (DDR1AD0)
Address 0x0272 Access: User read/write
(1)
1. Read: Anytime.
Write: Anytime.
76543210
R
DDR0AD07 DDR0AD06 DDR0AD05 DDR0AD04 DDR0AD03 DDR0AD02 DDR0AD01 DDR0AD00
W
Reset 00000000
Figure 2-69. Port AD0 Data Direction Register 0 (DDR0AD0)
Table 2-67. DDR0AD0 Register Field Descriptions
Field Description
7-0
DDR0AD0
Port AD0 data direction—
This register controls the data direction of pins 15 through 8.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
Address 0x0273 Access: User read/write
(1)
1. Read: Anytime.
Write: Anytime.
76543210
R
DDR1AD07 DDR1AD06 DDR1AD05 DDR1AD04 DDR1AD03 DDR1AD02 DDR1AD01 DDR1AD00
W
Reset 00000000
Figure 2-70. Port AD0 Data Direction Register 1 (DDR1AD0)