Datasheet

Chapter 2 Port Integration Module (S12XEPIMV1)
MC9S12XE-Family Reference Manual Rev. 1.25
Freescale Semiconductor 171
NOTE
Due to internal synchronization circuits, it can take up to 2 bus clock cycles
until the correct value is read on PTL or PTIL registers, when changing the
DDRL register.
2.3.96 Port L Reduced Drive Register (RDRL)
2.3.97 Port L Pull Device Enable Register (PERL)
Address 0x0373 Access: User read/write
(1)
1. Read: Anytime.
Write: Anytime.
76543210
R
RDRL7 RDRL6 RDRL5 RDRL4 RDRL3 RDRL2 RDRL1 RDRL0
W
Reset 00000000
Figure 2-94. Port L Reduced Drive Register (RDRL)
Table 2-91. RDRL Register Field Descriptions
Field Description
7-0
RDRL
Port L reduced drive—Select reduced drive for outputs
This register configures the drive strength of output pins 7 through 0 as either full or reduced independent of the
function used on the pins. If a pin is used as input this bit has no effect.
1 Reduced drive selected (approx. 1/5 of the full drive strength).
0 Full drive strength enabled.
Address 0x0374 Access: User read/write
(1)
1. Read: Anytime.
Write: Anytime.
76543210
R
PERL7 PERL6 PERL5 PERL4 PERL3 PERL2 PERL1 PERL0
W
Reset 11111111
Figure 2-95. Port L Pull Device Enable Register (PERL)
Table 2-92. PERL Register Field Descriptions
Field Description
7-0
PERL
Port L pull device enable—Enable pull devices on input pins
These bits configure whether a pull device is activated, if the associated pin is used as an input. This bit has no effect
if the pin is used as an output. Out of reset all pull devices are enabled.
1 Pull device enabled.
0 Pull device disabled.