Datasheet

Chapter 3 Memory Mapping Control (S12XMMCV4)
MC9S12XE-Family Reference Manual Rev. 1.25
Freescale Semiconductor 199
;many cases assemblers are “direct page aware” and can
;automatically select direct mode.
3.3.2.5 MMC Control Register (MMCCTL1)
Read: Anytime. In emulation modes read operations will return the data from the external bus. In all other
modes the data are read from this register.
Write: Refer to each bit description. In emulation modes write operations will also be directed to the
external bus.
CAUTION
XGATE write access to this register during an CPU access which makes use
of this register could lead to unexpected results.
Address: 0x0013 PRR
76543210
R
TGMRAMON
0
EEEIFRON PGMIFRON RAMHM EROMON ROMHM ROMON
W
Reset 00000EROMCTL 0 ROMCTL
= Unimplemented or Reserved
Figure 3-10. MMC Control Register (MMCCTL1)
Table 3-11. MMCCTL1 Field Descriptions
Field Description
7
TGMRAMON
EEE Tag RAM and FTM SCRATCH RAM visible in the memory map
Write: Anytime
This bit is used to made the EEE Tag RAM nd FTM SCRATCH RAM visible in the global memory map.
0 Not visible in the memory map.
1 Visible in the memory map.
5
EEEIFRON
EEE IFR visible in the memory map
Write: Anytime
This bit is used to made the IFR sector of EEE DATA FLASH visible in the global memory map.
0 Not visible in the memory map.
1 Visible in the memory map.
4
PGMIFRON
Program IFR visible in the memory map
Write: Anytime
This bit is used to made the IFR sector of the Program Flash visible in the global memory map.
0 Not visible in the memory map.
1 Visible in the memory map.
3
RAMHM
RAM only in higher Half of the memory map
Write: Once in normal and emulation modes and anytime in special modes
0 Accesses to $4000–$7FFF will be mapped to $14_4000-$14_7FFF in the global memory space (external
access).
1 Accesses to $4000–$7FFF will be mapped to $0F_C000-$0F_FFFF in the global memory space (RAM area).