Datasheet

Chapter 4 Memory Protection Unit (S12XMPUV1)
MC9S12XE-Family Reference Manual Rev. 1.25
228 Freescale Semiconductor
access is allowed or represents an access violation. If an access violation caused by the S12X CPU is
detected, the MPU module raises an access violation interrupt. If the MPU module detects an access
violation caused by a bus master other than the S12X CPU, it flags an access error condition to the
respective master. In addition to the restrictions defined for memory ranges in the MPU descriptors,
accesses to memory not covered by any MPU descriptor (even read accesses!) are considered access
violations.
Figure 4-1 shows a block diagram of the MPU module.
Figure 4-1. Block Diagram
4.1.3 Features
• Protects memory from undesired accesses coming from up to 3 bus masters
1
• Eight memory protection descriptors
— each descriptor can cover the full global memory map (8 MBytes)
— each descriptor has a granularity of 8 Bytes
1. Master 3 can be implemented or left out depending the chip configuration. Please refer to the Device Reference Manual for
information about the availability and function of Master 3.
Bus Interface
Data Access
Op-code Fetch
Status
Registers
CPU
MMC
MPU
Protection
Descriptors
Bus Interface
Data Access
“Master3”
Bus Interface
Data Access
Op-code Fetch
XGATE
Access Validation
Bus InterfaceBus InterfaceBus Interface
MPU Monitoring
Access Validation
MPU Monitoring
Access Validation
MPU Monitoring
Protection
Descriptors
Comparators
Comparators Comparators
Access Violation
Interrupt