Datasheet

Chapter 4 Memory Protection Unit (S12XMPUV1)
MC9S12XE-Family Reference Manual Rev. 1.25
234 Freescale Semiconductor
4.3.1.6 MPU Descriptor Register 0 (MPUDESC0)
Figure 4-8. MPU Descriptor Register 0 (MPUDESC0)
Read: Anytime
Write: Anytime
Table 4-8. MPUDESC0 Field Descriptions
A descriptor can be configured as valid for more than one bus-master at the same time by setting multiple
Master select bits to one. Setting all Master select bits of a descriptor to zero disables the descriptor.
4.3.1.7 MPU Descriptor Register 1 (MPUDESC1)
Figure 4-9. MPU Descriptor Register 1 (MPUDESC1)
Read: Anytime
Write: Anytime
Address: Module Base + 0x0006
76543210
R
MSTR0 MSTR1 MSTR2 MSTR3 LOW_ADDR[22:19]
W
Reset 1
(1)
1. initialized as set for descriptor 0 only, cleared for all others
1
1
1
1
1
(2)
2. initialized as set for descriptor 0 only, if MSTR3 is implemented on the device
0000
Field Description
7
MSTR0
Master 0 select bit — If this bit is set the descriptor is valid for bus master 0 (CPU in supervisor state).
6
MSTR1
Master 1 select bit — If this bit is set the descriptor is valid for bus master 1 (CPU in user state).
5
MSTR2
Master 2 select bit — If this bit is set the descriptor is valid for bus master 2 (XGATE).
4
MSTR3
Master 3 select bit — If this bit is set the descriptor is valid for bus master 3.
3–0
LOW_ADDR[
22:19]
Memory range lower boundary address bits — The LOW_ADDR[22:19] bits represent bits [22:19] of the
global memory address that is used as the lower boundary for the described memory range.
Address: Module Base + 0x0007
76543210
R
LOW_ADDR[18:11]
W
Reset 0 0 0 00000