Datasheet

Chapter 6 Interrupt (S12XINTV2)
MC9S12XE-Family Reference Manual Rev. 1.25
268 Freescale Semiconductor
6.3.2.3 Interrupt Request Configuration Address Register (INT_CFADDR)
Read: Anytime
Write: Anytime
6.3.2.4 Interrupt Request Configuration Data Registers (INT_CFDATA0–7)
The eight register window visible at addresses INT_CFDATA0–7 contains the configuration data for the
block of eight interrupt requests (out of 128) selected by the interrupt configuration address register
(INT_CFADDR) in ascending order. INT_CFDATA0 represents the interrupt configuration data register
of the vector with the lowest address in this block, while INT_CFDATA7 represents the interrupt
configuration data register of the vector with the highest address, respectively.
Table 6-6. XGATE Interrupt Priority Levels
Priority XILVL2 XILVL1 XILVL0 Meaning
0 0 0 Interrupt request is disabled
low 0 0 1 Priority level 1
0 1 0 Priority level 2
0 1 1 Priority level 3
1 0 0 Priority level 4
1 0 1 Priority level 5
1 1 0 Priority level 6
high 1 1 1 Priority level 7
Address: 0x0127
76543210
R
INT_CFADDR[7:4]
0000
W
Reset 0 0 0 10000
= Unimplemented or Reserved
Figure 6-5. Interrupt Configuration Address Register (INT_CFADDR)
Table 6-7. INT_CFADDR Field Descriptions
Field Description
7–4
INT_CFADDR[7:4]
Interrupt Request Configuration Data Register Select Bits — These bits determine which of the 128
configuration data registers are accessible in the 8 register window at INT_CFDATA0–7. The hexadecimal
value written to this register corresponds to the upper nibble of the lower byte of the address of the interrupt
vector, i.e., writing 0xE0 to this register selects the configuration data register block for the 8 interrupt vector
requests starting with vector at address (vector base + 0x00E0) to be accessible as INT_CFDATA0–7.
Note: Writing all 0s selects non-existing configuration registers. In this case write accesses to
INT_CFDATA0–7 will be ignored and read accesses will return all 0.