Datasheet

Chapter 8 S12X Debug (S12XDBGV3) Module
MC9S12XE-Family Reference Manual Rev. 1.25
308 Freescale Semiconductor
8.1.5 Block Diagram
Figure 8-1. Debug Module Block Diagram
8.2 External Signal Description
The S12XDBG sub-module features two external tag input signals. See Device User Guide (DUG) for the
mapping of these signals to device pins. These tag pins may be used for the external tagging in emulation
modes only.
8.3 Memory Map and Registers
8.3.1 Module Memory Map
A summary of the registers associated with the S12XDBG sub-block is shown in Table 8-2. Detailed
descriptions of the registers and bits are given in the subsections that follow.
Table 8-4. External System Pins Associated With S12XDBG
Pin Name Pin Functions Description
TAGHI
(See DUG)
TAGHI When instruction tagging is on, tags the high half of the instruction word being
read into the instruction queue.
TAGLO
(See DUG)
TAGLO When instruction tagging is on, tags the low half of the instruction word being
read into the instruction queue.
TAGLO
(See DUG)
Unconditional
Tagging Enable
In emulation modes, a low assertion on this pin in the 7th or 8th cycle after the
end of reset enables the Unconditional Tagging function.
CPU12X BUS
TRACE BUFFER
BUS INTERFACE
TRIGGER
EXTERNAL TAGHI / TAGLO
MATCH0
STATE
XGATE BUS
COMPARATOR B
COMPARATOR C
COMPARATOR D
COMPARATOR A
STATE SEQUENCER
MATCH1
MATCH2
MATCH3
TRACE
READ TRACE DATA (DBG READ DATA BUS)
CONTROL
SECURE
BREAKPOINT REQUESTS
COMPARATOR
MATCH CONTROL
XGATE S/W BREAKPOINT REQUEST
TRIGGER
TAG &
TRIGGER
CONTROL
LOGIC
TAGS
TAGHITS
STATE
CPU12X & XGATE