Datasheet

Chapter 8 S12X Debug (S12XDBGV3) Module
MC9S12XE-Family Reference Manual Rev. 1.25
Freescale Semiconductor 317
8.3.2.7 Debug State Control Registers
There is a dedicated control register for each of the state sequencer states 1 to 3 that determines if
transitions from that state are allowed, depending upon comparator matches or tag hits, and defines the
next state for the state sequencer following a match. The three debug state control registers are located at
the same address in the register address map (0x0027). Each register can be accessed using the COMRV
bits in DBGC1 to blend in the required register. The COMRV = 11 value blends in the match flag register
(DBGMFR).
8.3.2.7.1 Debug State Control Register 1 (DBGSCR1)
Read: If COMRV[1:0] = 00
Write: If COMRV[1:0] = 00 and S12XDBG is not armed.
This register is visible at 0x0027 only with COMRV[1:0] = 00. The state control register 1 selects the
targeted next state whilst in State1. The matches refer to the match channels of the comparator match
control logic as depicted in Figure 8-1 and described in Section 8.3.2.8.1. Comparators must be enabled
by setting the comparator enable bit in the associated DBGXCTL control register.
Table 8-21. State Control Register Access Encoding
COMRV Visible State Control Register
00 DBGSCR1
01 DBGSCR2
10 DBGSCR3
11 DBGMFR
Address: 0x0027
76543210
R0000
SC3 SC2 SC1 SC0
W
Reset 00000000
= Unimplemented or Reserved
Figure 8-9. Debug State Control Register 1 (DBGSCR1)
Table 8-22. DBGSCR1 Field Descriptions
Field Description
3–0
SC[3:0]
These bits select the targeted next state whilst in State1, based upon the match event.
Table 8-23. State1 Sequencer Next State Selection
SC[3:0] Description
0000 Any match triggers to state2
0001 Any match triggers to state3
0010 Any match triggers to Final State