Datasheet

Chapter 8 S12X Debug (S12XDBGV3) Module
MC9S12XE-Family Reference Manual Rev. 1.25
318 Freescale Semiconductor
The trigger priorities described in Table 8-42 dictate that in the case of simultaneous matches, the match
on the lower channel number (0,1,2,3) has priority. The SC[3:0] encoding ensures that a match leading to
final state has priority over all other matches.
8.3.2.7.2 Debug State Control Register 2 (DBGSCR2)
Read: If COMRV[1:0] = 01
Write: If COMRV[1:0] = 01 and S12XDBG is not armed.
This register is visible at 0x0027 only with COMRV[1:0] = 01. The state control register 2 selects the
targeted next state whilst in State2. The matches refer to the match channels of the comparator match
control logic as depicted in Figure 8-1 and described in Section 8.3.2.8.1. Comparators must be enabled
by setting the comparator enable bit in the associated DBGXCTL control register.
0011 Match2 triggers to State2....... Other matches have no effect
0100 Match2 triggers to State3....... Other matches have no effect
0101 Match2 triggers to Final State....... Other matches have no effect
0110 Match0 triggers to State2....... Match1 triggers to State3....... Other matches have no effect
0111 Match1 triggers to State3....... Match0 triggers Final State....... Other matches have no effect
1000 Match0 triggers to State2....... Match2 triggers to State3....... Other matches have no effect
1001 Match2 triggers to State3....... Match0 triggers Final State....... Other matches have no effect
1010 Match1 triggers to State2....... Match3 triggers to State3....... Other matches have no effect
1011 Match3 triggers to State3....... Match1 triggers to Final State....... Other matches have no effect
1100 Match3 has no effect....... All other matches (M0,M1,M2) trigger to State2
1101 Reserved. (No match triggers state sequencer transition)
1110 Reserved. (No match triggers state sequencer transition)
1111 Reserved. (No match triggers state sequencer transition)
Address: 0x0027
76543210
R0000
SC3 SC2 SC1 SC0
W
Reset 00000000
= Unimplemented or Reserved
Figure 8-10. Debug State Control Register 2 (DBGSCR2)
Table 8-24. DBGSCR2 Field Descriptions
Field Description
3–0
SC[3:0]
These bits select the targeted next state whilst in State2, based upon the match event.
Table 8-25. State2 —Sequencer Next State Selection
SC[3:0] Description
0000 Any match triggers to state1
Table 8-23. State1 Sequencer Next State Selection (continued)
SC[3:0] Description