Datasheet

Chapter 10 XGATE (S12XGATEV3)
MC9S12XE-Family Reference Manual Rev. 1.25
Freescale Semiconductor 369
10.3.1.11 XGATE Condition Code Register (XGCCR)
The XGCCR register (Figure 10-13) provides access to the RISC core’s condition code register.
Read: In debug mode if unsecured and not idle (XGCHID ≠ 0x00)
Write: In debug mode if unsecured and not idle (XGCHID ≠ 0x00)
Table 10-12. XGSEM Field Descriptions
Field Description
15–8
XGSEMM[7:0]
Semaphore Mask — These bits control the write access to the XGSEM bits.
Read:
These bits will always read "0".
Write:
0 Disable write access to the XGSEM in the same bus cycle
1 Enable write access to the XGSEM in the same bus cycle
7–0
XGSEM[7:0]
Semaphore Bits — These bits indicate whether a semaphore is locked by the S12X_CPU. A semaphore can
be attempted to be set by writing a "1" to the XGSEM bit and to the corresponding XGSEMM bit in the same
write access. Only unlocked semaphores can be set. A semaphore can be cleared by writing a "0" to the
XGSEM bit and a "1" to the corresponding XGSEMM bit in the same write access.
Read:
0 Semaphore is unlocked or locked by the RISC core
1 Semaphore is locked by the S12X_CPU
Write:
0 Clear semaphore if it was locked by the S12X_CPU
1 Attempt to lock semaphore by the S12X_CPU
Module Base +0x001D
76543210
R0000
XGN XGZ XGV XGC
W
Reset 00000000
= Unimplemented or Reserved
Figure 10-13. XGATE Condition Code Register (XGCCR)
Table 10-13. XGCCR Field Descriptions
Field Description
3
XGN
Sign Flag — The RISC core’s Sign flag
2
XGZ
Zero Flag — The RISC core’s Zero flag
1
XGV
Overflow Flag — The RISC core’s Overflow flag
0
XGC
Carry Flag — The RISC core’s Carry flag