Datasheet

Chapter 10 XGATE (S12XGATEV3)
MC9S12XE-Family Reference Manual Rev. 1.25
372 Freescale Semiconductor
10.3.1.16 XGATE Register 4 (XGR4)
The XGR4 register (Figure 10-18) provides access to the RISC core’s register 4.
Read: In debug mode if unsecured and not idle (XGCHID ≠ 0x00)
Write: In debug mode if unsecured and not idle (XGCHID ≠ 0x00)
10.3.1.17 XGATE Register 5 (XGR5)
The XGR5 register (Figure 10-19) provides access to the RISC core’s register 5.
Read: In debug mode if unsecured and not idle (XGCHID ≠ 0x00)
Write: In debug mode if unsecured and not idle (XGCHID ≠ 0x00)
Module Base +0x00028
1514131211109876543210
R
XGR4
W
Reset 0000000000000000
Figure 10-18. XGATE Register 4 (XGR4)
Table 10-18. XGR4 Field Descriptions
Field Description
15–0
XGR4[15:0]
XGATE Register 4 — The RISC core’s register 4
Module Base +0x0002A
1514131211109876543210
R
XGR5
W
Reset 0000000000000000
Figure 10-19. XGATE Register 5 (XGR5)
Table 10-19. XGR5 Field Descriptions
Field Description
15–0
XGR5[15:0]
XGATE Register 5 — The RISC core’s register 5