Datasheet

Chapter 10 XGATE (S12XGATEV3)

MC9S12XE-Family Reference Manual Rev. 1.25

Freescale Semiconductor 393

Operation

RS1 & RS2 ⇒ RD

RD & IMM16 ⇒ RD (translates to ANDL RD, #IMM16[7:0]; ANDH RD, #IMM16[15:8])

Performs a bit wise logical AND of two 16 bit values and stores the result in the destination register RD.

NOTE

When using immediate addressing mode (AND RD, #IMM16), the Z-ﬂag

of the ﬁrst instruction (ANDL RD, #IMM16[7:0]) is not considered by the

second instruction (ANDH RD, #IMM16[15:8]).

⇒ Don’t rely on the Z-Flag.

CCR Effects

Code and CPU Cycles

AND

Logical AND

AND

NZVC

∆∆0—

N: Set if bit 15 of the result is set; cleared otherwise.

Z: Set if the result is $0000; cleared otherwise.

Refer to ANDH instruction for #IMM16 operations.

V: 0; cleared.

C: Not affected.

Source Form

Address

Mode

Machine Code Cycles

AND RD, RS1, RS2 TRI 0 0 0 1 0 RD RS1 RS2 0 0 P

AND RD, #IMM16 IMM8 1 0 0 0 0 RD IMM16[7:0] P

IMM8 1 0 0 0 1 RD IMM16[15:8] P