Datasheet

Chapter 11 S12XE Clocks and Reset Generator (S12XECRGV1)

MC9S12XE-Family Reference Manual Rev. 1.25

484 Freescale Semiconductor

11.3.2.10 Reserved Register (FORBYP)

NOTE

This reserved register is designed for factory test purposes only, and is not

intended for general user access. Writing to this register when in special

modes can alter the S12XECRG’s functionality.

Read: Always read $00 except in special modes

Write: Only in special modes

11.3.2.11 Reserved Register (CTCTL)

NOTE

This reserved register is designed for factory test purposes only, and is not

intended for general user access. Writing to this register when in special test

modes can alter the S12XECRG’s functionality.

Read: Always read $00 except in special modes

111 2

1. OSCCLK cycles are referenced from the previous COP time-out reset

(writing $55/$AA to the ARMCOP register)

Module Base + 0x0009

76543210

R00000000

Reset 0 0 0 00000

= Unimplemented or Reserved

Figure 11-12. Reserved Register (FORBYP)

Module Base + 0x000A

76543210

R00000000

Reset 0 0 0 00000

= Unimplemented or Reserved

Figure 11-13. Reserved Register (CTCTL)

Table 11-13. COP Watchdog Rates

(1)

CR2 CR1 CR0

OSCCLK

Cycles to Timeout