Datasheet

Chapter 13 Analog-to-Digital Converter (ADC12B16CV1)
MC9S12XE-Family Reference Manual Rev. 1.25
508 Freescale Semiconductor
13.3.2 Register Descriptions
This section describes in address order all the ADC12B16C registers and their individual bits.
13.3.2.1 ATD Control Register 0 (ATDCTL0)
Writes to this register will abort current conversion sequence.
Read: Anytime
Write: Anytime, in special modes always write 0 to Reserved Bit 7.
0x0024 ATDDR10
R
See Section 13.3.2.12.1, “Left Justified Result Data (DJM=0)”
and Section 13.3.2.12.2, “Right Justified Result Data (DJM=1)”
W
0x0026 ATDDR11
R
See Section 13.3.2.12.1, “Left Justified Result Data (DJM=0)”
and Section 13.3.2.12.2, “Right Justified Result Data (DJM=1)”
W
0x0028 ATDDR12
R
See Section 13.3.2.12.1, “Left Justified Result Data (DJM=0)”
and Section 13.3.2.12.2, “Right Justified Result Data (DJM=1)”
W
0x002A ATDDR13
R
See Section 13.3.2.12.1, “Left Justified Result Data (DJM=0)”
and Section 13.3.2.12.2, “Right Justified Result Data (DJM=1)”
W
0x002C ATDDR14
R
See Section 13.3.2.12.1, “Left Justified Result Data (DJM=0)”
and Section 13.3.2.12.2, “Right Justified Result Data (DJM=1)”
W
0x002E ATDDR15
R
See Section 13.3.2.12.1, “Left Justified Result Data (DJM=0)”
and Section 13.3.2.12.2, “Right Justified Result Data (DJM=1)”
W
Module Base + 0x0000
76543210
R
Reserved
000
WRAP3 WRAP2 WRAP1 WRAP0
W
Reset 0 0 0 01111
= Unimplemented or Reserved
Figure 13-3. ATD Control Register 0 (ATDCTL0)
Table 13-2. ATDCTL0 Field Descriptions
Field Description
3-0
WRAP[3-0]
Wrap Around Channel Select Bits — These bits determine the channel for wrap around when doing multi-
channel conversions. The coding is summarized in Table 13-3.
Table 13-3. Multi-Channel Wrap Around Coding
WRAP3 WRAP2 WRAP1 WRAP0
Multiple Channel Conversions (MULT = 1)
Wraparound to AN0 after Converting
0000 Reserved
(1)
Address Name Bit 7 6 5 4 3 2 1 Bit 0
= Unimplemented or Reserved
Figure 13-2. ADC12B16C Register Summary (Sheet 3 of 3)