Datasheet

Chapter 13 Analog-to-Digital Converter (ADC12B16CV1)
MC9S12XE-Family Reference Manual Rev. 1.25
512 Freescale Semiconductor
13.3.2.4 ATD Control Register 3 (ATDCTL3)
Writes to this register will abort current conversion sequence.
Read: Anytime
Write: Anytime
1
ASCIE
ATD Sequence Complete Interrupt Enable
0 ATD Sequence Complete interrupt requests are disabled.
1 ATD Sequence Complete interrupt will be requested whenever SCF=1 is set.
0
ACMPIE
ATD Compare Interrupt Enable — If automatic compare is enabled for conversion n (CMPE[n]=1 in ATDCMPE
register) this bit enables the compare interrupt. If the CCF[n] flag is set (showing a successful compare for
conversion n), the compare interrupt is triggered.
0 ATD Compare interrupt requests are disabled.
1 For the conversions in a sequence for which automatic compare is enabled (CMPE[n]=1), ATD Compare
Interrupt will be requested whenever any of the respective CCF flags is set.
Table 13-8. External Trigger Configurations
ETRIGLE ETRIGP External Trigger Sensitivity
0 0 Falling edge
0 1 Rising edge
1 0 Low level
1 1 High level
Module Base + 0x0003
76543210
R
DJM S8C S4C S2C S1C FIFO FRZ1 FRZ0
W
Reset 0 0 1 00000
= Unimplemented or Reserved
Figure 13-6. ATD Control Register 3 (ATDCTL3)
Field Description
7
DJM
Result Register Data Justification — Result data format is always unsigned. This bit controls justification of
conversion data in the result registers.
0 Left justified data in the result registers.
1 Right justified data in the result registers.
Table 13-10 gives examples ATD results for an input signal range between 0 and 5.12 Volts.
Table 13-9. ATDCTL3 Field Descriptions
Table 13-7. ATDCTL2 Field Descriptions (continued)
Field Description