Datasheet

Chapter 14 Enhanced Capture Timer (ECT16B8CV3)
MC9S12XE-Family Reference Manual Rev. 1.25
Freescale Semiconductor 537
14.3.2.4 Output Compare 7 Data Register (OC7D)
Read or write: Anytime
All bits reset to zero.
14.3.2.5 Timer Count Register (TCNT)
Table 14-4. OC7M Field Descriptions
Field Description
7:0
OC7M[7:0]
Output Compare Mask Action for Channel 7:0
A channel 7 event, which can be a counter overflow when TTOV[7] is set or a successful output compare
on channel 7, overrides any channel 6:0 compares. For each OC7M bit that is set,the output compare
action reflects the corresponding OC7D bit.
0 The corresponding OC7Dx bit in the output compare 7 data register will not be transferred to the timer port on
a channel 7 event, even if the corresponding pin is setup for output compare.
1 The corresponding OC7Dx bit in the output compare 7 data register will be transferred to the timer port on a
channel 7 event.
Note: The corresponding channel must also be setup for output compare (IOSx = 1 andOCPDx = 0) for data to
be transferred from the output compare 7 data register to the timer port.
Module Base + 0x0003
76543210
R
OC7D7 OC7D6 OC7D5 OC7D4 OC7D3 OC7D2 OC7D1 OC7D0
W
Reset 00000000
Figure 14-6. Output Compare 7 Data Register (OC7D)
Table 14-5. OC7D Field Descriptions
Field Description
7:0
OC7D[7:0]
Output Compare 7 Data Bits — A channel 7 event, which can be a counter overflow when TTOV[7] is set or A
channel 7 output compare can cause bits in the output compare 7 data register to transfer to the timer port data
register depending on the output compare 7 mask register.
Module Base + 0x0004
15 14 13 12 11 10 9 8
R
TCNT15 TCNT14 TCNT13 TCNT12 TCNT11 TCNT10 TCNT9 TCNT8
W
Reset 00000000
Figure 14-7. Timer Count Register High (TCNT)