Datasheet

Chapter 14 Enhanced Capture Timer (ECT16B8CV3)
MC9S12XE-Family Reference Manual Rev. 1.25
544 Freescale Semiconductor
Figure 14-17. The TCNT cycle diagram under TCRE=1 condition
Table 14-15. TSCR2 Field Descriptions
Field Description
7
TOI
Timer Overflow Interrupt Enable
0 Timer overflow interrupt disabled.
1 Hardware interrupt requested when TOF flag set.
3
TCRE
Timer Counter Reset Enable — This bit allows the timer counter to be reset by a successful channel 7 output
compare. This mode of operation is similar to an up-counting modulus counter.
0 Counter reset disabled and counter free runs.
1 Counter reset by a successful output compare on channel 7.
Note: If register TC7 = 0x0000 and TCRE = 1, then the TCNT register will stay at 0x0000 continuously. If register
TC7 = 0xFFFF and TCRE = 1, the TOF flag will never be set when TCNT is reset from 0xFFFF to 0x0000.
Note: TCRE=1 and TC7!=0, the TCNT cycle period will be TC7 x "prescaler counter width" + "1 Bus Clock".
When TCRE is set and TC7 is not equal to 0, TCNT will cycle from 0 to TC7. When TCNT reaches TC7
value, it will last only one bus cycle then reset to 0. for a more detail explanation please refer to Figure 14-
17.
Note: in Figure 14-17,if PR[2:0] is equal to 0, one prescaler counter equal to one bus clock
2:0
PR[2:0]
Timer Prescaler Select — These three bits specify the division rate of the main Timer prescaler when the PRNT
bit of register TSCR1 is set to 0. The newly selected prescale factor will not take effect until the next synchronized
edge where all prescale counter stages equal zero. See Table 14-16.
Table 14-16. Prescaler Selection
PR2 PR1 PR0 Prescale Factor
000 1
001 2
010 4
011 8
100 16
101 32
110 64
1 1 1 128
TC7
0
1
----- TC7-1 TC7
0
TC7 event
TC7 event
prescaler
counter
1 bus
clock