Datasheet

Chapter 14 Enhanced Capture Timer (ECT16B8CV3)
MC9S12XE-Family Reference Manual Rev. 1.25
Freescale Semiconductor 577
14.4.2 Reset
The reset state of each individual bit is listed within the register description section (Section 14.3,
“Memory Map and Register Definition”) which details the registers and their bit-fields.
14.4.3 Interrupts
This section describes interrupts originated by the ECT block. The MCU must service the interrupt
requests. Table 14-39 lists the interrupts generated by the ECT to communicate with the MCU.
Table 14-39. ECT Interrupts
The ECT only originates interrupt requests. The following is a description of how the module makes a
request and how the MCU should acknowledge that request. The interrupt vector offset and interrupt
number are chip dependent.
14.4.3.1 Channel [7:0] Interrupt
This active high output will be asserted by the module to request a timer channel 7–0 interrupt to be
serviced by the system controller.
14.4.3.2 Modulus Counter Interrupt
This active high output will be asserted by the module to request a modulus counter underflow interrupt to
be serviced by the system controller.
14.4.3.3 Pulse Accumulator B Overflow Interrupt
This active high output will be asserted by the module to request a timer pulse accumulator B overflow
interrupt to be serviced by the system controller.
14.4.3.4 Pulse Accumulator A Input Interrupt
This active high output will be asserted by the module to request a timer pulse accumulator A input
interrupt to be serviced by the system controller.
Interrupt Source Description
Timer channel 7–0 Active high timer channel interrupts 7–0
Modulus counter underflow Active high modulus counter interrupt
Pulse accumulator B overflow Active high pulse accumulator B interrupt
Pulse accumulator A input Active high pulse accumulator A input interrupt
Pulse accumulator A overflow Pulse accumulator overflow interrupt
Timer overflow Timer 0verflow interrupt