Datasheet

Chapter 15 Inter-Integrated Circuit (IICV3) Block Description

MC9S12XE-Family Reference Manual Rev. 1.25

580 Freescale Semiconductor

• General Call Address detection

• Compliant to ten-bit address

15.1.2 Modes of Operation

The IIC functions the same in normal, special, and emulation modes. It has two low power modes: wait

and stop modes.

15.1.3 Block Diagram

The block diagram of the IIC module is shown in Figure 15-1.

Figure 15-1. IIC Block Diagram

15.2 External Signal Description

The IICV3 module has two external pins.

15.2.1 IIC_SCL — Serial Clock Line Pin

This is the bidirectional serial clock line (SCL) of the module, compatible to the IIC bus speciﬁcation.

15.2.2 IIC_SDA — Serial Data Line Pin

This is the bidirectional serial data line (SDA) of the module, compatible to the IIC bus speciﬁcation.

In/Out

Data

Shift

Address

Compare

SDA

Interrupt

Clock

Control

Start

Stop

Arbitration

Control

SCL

bus_clock

IIC

Registers