Datasheet

Chapter 15 Inter-Integrated Circuit (IICV3) Block Description
MC9S12XE-Family Reference Manual Rev. 1.25
582 Freescale Semiconductor
This register contains the address the IIC bus will respond to when addressed as a slave; note that it is not
the address sent on the bus during the address transfer.
15.3.1.2 IIC Frequency Divider Register (IBFD)
Read and write anytime
Table 15-2. IBAD Field Descriptions
Field Description
7:1
ADR[7:1]
Slave Address — Bit 1 to bit 7 contain the specific slave address to be used by the IIC bus module.The default
mode of IIC bus is slave mode for an address match on the bus.
0
Reserved
Reserved — Bit 0 of the IBAD is reserved for future compatibility. This bit will always read 0.
Module Base + 0x0001
76543210
R
IBC7 IBC6 IBC5 IBC4 IBC3 IBC2 IBC1 IBC0
W
Reset 0 0 0 00000
= Unimplemented or Reserved
Figure 15-4. IIC Bus Frequency Divider Register (IBFD)
Table 15-3. IBFD Field Descriptions
Field Description
7:0
IBC[7:0]
I Bus Clock Rate 7:0 — This field is used to prescale the clock for bit rate selection. The bit clock generator is
implemented as a prescale divider — IBC7:6, prescaled shift register — IBC5:3 select the prescaler divider and
IBC2-0 select the shift register tap point. The IBC bits are decoded to give the tap and prescale values as shown
in Table 15-4.
Table 15-4. I-Bus Tap and Prescale Values
IBC2-0
(bin)
SCL Tap
(clocks)
SDA Tap
(clocks)
000 5 1
001 6 1
010 7 2
011 8 2
100 9 3
101 10 3
110 12 4
111 15 4