Datasheet

Chapter 15 Inter-Integrated Circuit (IICV3) Block Description
MC9S12XE-Family Reference Manual Rev. 1.25
602 Freescale Semiconductor
attempt to engage the bus is failed. When considering these cases, the slave service routine should test the
IBAL first and the software should clear the IBAL bit if it is set.
Figure 15-15. Flow-Chart of Typical IIC Interrupt Routine
Clear
Master
Mode
?
Tx/Rx
?
Last Byte
Transmitted
?
RXAK=0
?
End Of
Addr Cycle
(Master Rx)
?
Write Next
Byte To IBDR
Switch To
Rx Mode
Dummy Read
From IBDR
Generate
Stop Signal
Read Data
From IBDR
And Store
Set TXAK =1
Generate
Stop Signal
2nd Last
Byte To Be Read
?
Last
Byte To Be Read
?
Arbitration
Lost
?
Clear IBAL
IAAS=1
?
IAAS=1
?
SRW=1
?
TX/RX
?
Set TX
Mode
Write Data
To IBDR
Set RX
Mode
Dummy Read
From IBDR
ACK From
Receiver
?
Tx Next
Byte
Read Data
From IBDR
And Store
Switch To
Rx Mode
Dummy Read
From IBDR
RTI
YN
Y
Y
Y
Y
Y
Y
Y
N
N
N
N
N
N
N
N
Y
TX RX
RX
TX
(Write)
(Read)
N
IBIF
Data Transfer
Y
Y
10-bit
address?
N
N
7-bit address transfer
Y
10-bit address transfer
Mode
set RX
Dummy Read
From IBDR
N
set TX
Mode
Write Data
To IBDR
Y
IBDR==
11110xx1?