Datasheet

Chapter 17 Periodic Interrupt Timer (S12PIT24B8CV2)
MC9S12XE-Family Reference Manual Rev. 1.25
Freescale Semiconductor 665
17.3.0.3 PIT Channel Enable Register (PITCE)
Read: Anytime
Write: Anytime
17.3.0.4 PIT Multiplex Register (PITMUX)
Read: Anytime
Write: Anytime
Table 17-3. PITFLT Field Descriptions
Field Description
7:0
PFLT[7:0]
PIT Force Load Bits for Timer 7-0 — These bits have only an effect if the corresponding timer channel (PCE
set) is enabled and if the PIT module is enabled (PITE set). Writing a one into a PFLT bit loads the corresponding
16-bit timer load register into the 16-bit timer down-counter. Writing a zero has no effect. Reading these bits will
always return zero.
Module Base + 0x0002
76543210
R
PCE7 PCE6 PCE5 PCE4 PCE3 PCE2 PCE1 PCE0
W
Reset 0 0 0 00000
Figure 17-5. PIT Channel Enable Register (PITCE)
Table 17-4. PITCE Field Descriptions
Field Description
7:0
PCE[7:0]
PIT Enable Bits for Timer Channel 7:0 — These bits enable the PIT channels 7-0. If PCE is cleared, the PIT
channel is disabled and the corresponding flag bit in the PITTF register is cleared. When PCE is set, and if the
PIT module is enabled (PITE = 1) the 16-bit timer counter is loaded with the start count value and starts down-
counting.
0 The corresponding PIT channel is disabled.
1 The corresponding PIT channel is enabled.
Module Base + 0x0003
76543210
R
PMUX7 PMUX6 PMUX5 PMUX4 PMUX3 PMUX2 PMUX1 PMUX0
W
Reset 0 0 0 00000
Figure 17-6. PIT Multiplex Register (PITMUX)