Datasheet

Chapter 18 Periodic Interrupt Timer (S12PIT24B4CV2)
MC9S12XE-Family Reference Manual Rev. 1.25
678 Freescale Semiconductor
• Run mode
This is the basic mode of operation.
• Wait mode
PIT operation in wait mode is controlled by the PITSWAI bit located in the PITCFLMT register.
In wait mode, if the bus clock is globally enabled and if the PITSWAI bit is clear, the PIT operates
like in run mode. In wait mode, if the PITSWAI bit is set, the PIT module is stalled.
• Stop mode
In full stop mode or pseudo stop mode, the PIT module is stalled.
• Freeze mode
PIT operation in freeze mode is controlled by the PITFRZ bit located in the PITCFLMT register.
In freeze mode, if the PITFRZ bit is clear, the PIT operates like in run mode. In freeze mode, if the
PITFRZ bit is set, the PIT module is stalled.
18.1.4 Block Diagram
Figure 18-1 shows a block diagram of the PIT module.
Figure 18-1. PIT24B4C Block Diagram
18.2 External Signal Description
The PIT module has no external pins.
18.3 Register Definition
This section consists of register descriptions in address order of the PIT. Each description includes a
standard register diagram with an associated figure number. Details of register bit and field function follow
the register diagrams, in bit order.
Time-Out 0
Time-Out 1
Time-Out 2
Time-Out 3
16-Bit Timer 1
16-Bit Timer 3
16-Bit Timer 0
16-Bit Timer 2
Bus Clock
Micro Time
Base 0
Micro
Time
Base 1
Interrupt 0
Trigger 0
Interface
Interrupt 1
Trigger 1
Interface
Interrupt 2
Trigger 2
Interface
Interrupt 3
Trigger 3
Interface
8-Bit
Micro Timer 0
8-Bit
Micro Timer 1