Datasheet

Chapter 18 Periodic Interrupt Timer (S12PIT24B4CV2)

MC9S12XE-Family Reference Manual Rev. 1.25

Freescale Semiconductor 685

18.3.0.8 PIT Load Register 0 to 3 (PITLD0–3)

Read: Anytime

Write: Anytime

Table 18-8. PITMTLD0–1 Field Descriptions

Field Description

7:0

PMTLD[7:0]

PIT Micro Timer Load Bits 7:0 — These bits set the 8-bit modulus down-counter load value of the micro timers.

Writing a new value into the PITMTLD register will not restart the timer. When the micro timer has counted down

to zero, the PMTLD register value will be loaded. The PFLMT bits in the PITCFLMT register can be used to

immediately update the count register with the new value if an immediate load is desired.

Module Base + 0x0008, 0x0009

15 14 13 12 11 10 9876543210

PLD15 PLD14 PLD13 PLD12 PLD11 PLD10 PLD9 PLD8 PLD7 PLD6 PLD5 PLD4 PLD3 PLD2 PLD1 PLD0

Reset 0000000000000000

Figure 18-11. PIT Load Register 0 (PITLD0)

Module Base + 0x000C, 0x000D

15 14 13 12 11 10 9876543210

PLD15 PLD14 PLD13 PLD12 PLD11 PLD10 PLD9 PLD8 PLD7 PLD6 PLD5 PLD4 PLD3 PLD2 PLD1 PLD0

Reset 0000000000000000

Figure 18-12. PIT Load Register 1 (PITLD1)

Module Base + 0x0010, 0x0011

15 14 13 12 11 10 9876543210

PLD15 PLD14 PLD13 PLD12 PLD11 PLD10 PLD9 PLD8 PLD7 PLD6 PLD5 PLD4 PLD3 PLD2 PLD1 PLD0

Reset 0000000000000000

Figure 18-13. PIT Load Register 2 (PITLD2)

Module Base + 0x0014, 0x0015

15 14 13 12 11 10 9876543210

PLD15 PLD14 PLD13 PLD12 PLD11 PLD10 PLD9 PLD8 PLD7 PLD6 PLD5 PLD4 PLD3 PLD2 PLD1 PLD0

Reset 0000000000000000

Figure 18-14. PIT Load Register 3 (PITLD3)