Datasheet

Chapter 20 Serial Communication Interface (S12SCIV5)
MC9S12XE-Family Reference Manual Rev. 1.25
732 Freescale Semiconductor
20.3.2.4 SCI Alternative Control Register 1 (SCIACR1)
Read: Anytime, if AMAP = 1
Write: Anytime, if AMAP = 1
Module Base + 0x0001
76543210
R
RXEDGIE
00000
BERRIE BKDIE
W
Reset 0 0 0 00000
= Unimplemented or Reserved
Figure 20-7. SCI Alternative Control Register 1 (SCIACR1)
Table 20-7. SCIACR1 Field Descriptions
Field Description
7
RSEDGIE
Receive Input Active Edge Interrupt Enable — RXEDGIE enables the receive input active edge interrupt flag,
RXEDGIF, to generate interrupt requests.
0 RXEDGIF interrupt requests disabled
1 RXEDGIF interrupt requests enabled
1
BERRIE
Bit Error Interrupt Enable — BERRIE enables the bit error interrupt flag, BERRIF, to generate interrupt
requests.
0 BERRIF interrupt requests disabled
1 BERRIF interrupt requests enabled
0
BKDIE
Break Detect Interrupt Enable — BKDIE enables the break detect interrupt flag, BKDIF, to generate interrupt
requests.
0 BKDIF interrupt requests disabled
1 BKDIF interrupt requests enabled