Datasheet

Chapter 21 Serial Peripheral Interface (S12SPIV5)

MC9S12XE-Family Reference Manual Rev. 1.25

Freescale Semiconductor 771

Table 21-9. SPIF Interrupt Flag Clearing Sequence

Table 21-10. SPTEF Interrupt Flag Clearing Sequence

XFRW Bit SPIF Interrupt Flag Clearing Sequence

0 Read SPISR with SPIF == 1

then

Read SPIDRL

1 Read SPISR with SPIF == 1

then

Byte Read SPIDRL

(1)

1. Data in SPIDRH is lost in this case.

Byte Read SPIDRH

(2)

2. SPIDRH can be read repeatedly without any effect on SPIF. SPIF Flag is cleared only by the read

of SPIDRL after reading SPISR with SPIF == 1.

Byte Read SPIDRL

Word Read (SPIDRH:SPIDRL)

XFRW Bit SPTEF Interrupt Flag Clearing Sequence

0 Read SPISR with SPTEF == 1

then

Write to SPIDRL

(1)

1. Any write to SPIDRH or SPIDRL with SPTEF == 0 is effectively ignored.

1 Read SPISR with SPTEF == 1

then

Byte Write to SPIDRL

1(2)

2. Data in SPIDRH is undeﬁned in this case.

Byte Write to SPIDRH

1(3)

3. SPIDRH can be written repeatedly without any effect on SPTEF. SPTEF Flag is cleared only by

writing to SPIDRL after reading SPISR with SPTEF == 1.

Byte Write to SPIDRL

Word Write to (SPIDRH:SPIDRL)