Datasheet

Chapter 22 Timer Module (TIM16B8CV2) Block Description
MC9S12XE-Family Reference Manual Rev. 1.25
798 Freescale Semiconductor
22.3.2.7 Timer Toggle On Overflow Register 1 (TTOV)
Read: Anytime
Write: Anytime
4
TFFCA
Timer Fast Flag Clear All
0 Allows the timer flag clearing to function normally.
1 For TFLG1(0x000E), a read from an input capture or a write to the output compare channel (0x0010–0x001F)
causes the corresponding channel flag, CnF, to be cleared. For TFLG2 (0x000F), any access to the TCNT
register (0x0004, 0x0005) clears the TOF flag. Any access to the PACNT registers (0x0022, 0x0023) clears
the PAOVF and PAIF flags in the PAFLG register (0x0021). This has the advantage of eliminating software
overhead in a separate clear sequence. Extra care is required to avoid accidental flag clearing due to
unintended accesses.
3
PRNT
Precision Timer
0 Enables legacy timer. PR0, PR1, and PR2 bits of the TSCR2 register are used for timer counter prescaler
selection.
1 Enables precision timer. All bits of the PTPSR register are used for Precision Timer Prescaler Selection, and
all bits.
This bit is writable only once out of reset.
Module Base + 0x0007
76543210
R
TOV7 TOV6 TOV5 TOV4 TOV3 TOV2 TOV1 TOV0
W
Reset 00000000
Figure 22-13. Timer Toggle On Overflow Register 1 (TTOV)
Table 22-7. TTOV Field Descriptions
Field Description
7:0
TOV[7:0]
Toggle On Overflow Bits — TOVx toggles output compare pin on overflow. This feature only takes effect when
in output compare mode. When set, it takes precedence over forced output compare but not channel 7 override
events.
0 Toggle output compare pin on overflow feature disabled.
1 Toggle output compare pin on overflow feature enabled.
Table 22-6. TSCR1 Field Descriptions (continued)
Field Description