Datasheet

Chapter 23 Voltage Regulator (S12VREGL3V3V1)
MC9S12XE-Family Reference Manual Rev. 1.25
Freescale Semiconductor 825
The period can be calculated as follows depending of APICLK:
Period = 2*(APIR[15:0] + 1) * 0.1 ms or period = 2*(APIR[15:0] + 1) * bus clock period
23.3.2.6 Reserved 06
The Reserved 06 is reserved for test purposes.
23.3.2.7 High Temperature Trimming Register (VREGHTTR)
The VREGHTTR register allows to trim the VREG temperature sense.
Fiption
1 FFFF 131072 * bus clock period
1. When trimmed within specified accuracy. See electrical specifications for details.
0x02F6
76543210
R00000000
W
Reset 0 0 0 00000
= Unimplemented or Reserved
Figure 23-8. Reserved 06
0x02F7
76543210
R
HTOEN
000
HTTR3 HTTR2 HTTR1 HTTR0
W
Reset 0 0 0 0 0
1
0
1
0
1
0
1
1. Reset value is either 0 or preset by factory. See Section 1 (Device Overview) for details.
= Unimplemented or Reserved
Figure 23-9. VREGHTTR
Table 23-10. VREGHTTR field descriptions
Field Description
7
HTOEN
High Temperature Offset Enable Bit — If set the temperature sense offset is enabled
0 The temperature sense offset is disabled
1 The temperature sense offset is enabled
3–0
HTTR[3:0]
High Temperature Trimming Bits — See Table 23-11 for trimming effects.
Table 23-11. Trimming Effect
Bit Trimming Effect
HTTR[3] Increases V
HT
twice of HTTR[2]
Table 23-9. Selectable Autonomous Periodical Interrupt Periods (continued)
APICLK APIR[15:0] Selected Period