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Chapter 1 Device Overview MC9S12XE-Family

MC9S12XE-Family Reference Manual Rev. 1.25

84 Freescale Semiconductor

1.6.3 Effects of Reset

When a reset occurs, MCU registers and control bits are initialized. Refer to the respective block

descriptions for register reset states.

On each reset, the Flash module executes a reset sequence to load Flash configuration registers and

initialize the buffer RAM EEE partition, if required.

1.6.3.1 Flash Conﬁguration Reset Sequence (Core Hold Phase)

On each reset, the Flash module will hold CPU activity while loading Flash module registers and

conﬁguration from the Flash memory. The duration of this phase is given as t

RST

in the device electrical

parameter speciﬁcation. If double faults are detected in the reset phase, Flash module protection and

security may be active on leaving reset. This is explained in more detail in the Flash module section.

1.6.3.2 EEE Reset Sequence Phase (Core Active Phase)

During this phase of the reset sequence (following on from the core hold phase) the CPU can execute

instructions while the FTM initialization completes and, if conﬁgured for EEE operation, the EEE RAM

Vector base+ $4E $27 TIM timer channel 3 I bit TIE (C3I) No Yes

Vector base + $4C $26 TIM timer channel 4 I bit TIE (C4I) No Yes

Vector base+ $4A $25 TIM timer channel 5 I bit TIE (C5I) No Yes

Vector base+ $48 $24 TIM timer channel 6 I bit TIE (C6I) No Yes

Vector base+ $46 $23 TIM timer channel 7 I bit TIE (C7I) No Yes

Vector base+ $44 $22 TIM timer overﬂow I bit TSRC2 (TOF) No Yes

Vector base + $42 $21 TIM Pulse accumulator A overﬂow I bit PACTL (PAOVI) No Yes

Vector base+ $40 $20 TIM Pulse accumulator input edge I bit PACTL (PAI) No Yes

Vector base + $3E $1F ATD0 Compare Interrupt I bit ATD0CTL2 (ACMPIE) Yes Yes

Vector base + $3C $1E ATD1 Compare Interrupt I bit ATD1CTL2 (ACMPIE) Yes Yes

Vector base+ $18

Vector base + $3A

Reserved

Vector base + $16 — XGATE software error interrupt None None No Yes

Vector base + $14 — MPU Access Error None None No No

Vector base + $12 — System Call Interrupt (SYS) — None — —

Vector base + $10 — Spurious interrupt — None — —

1. 16 bits vector address based

2. For detailed description of XGATE channel ID refer to XGATE Block Guide

Table 1-14. Interrupt Vector Locations (Sheet 4 of 4)

Vector Address

(1)

XGATE

Channel

(2)

Interrupt Source

CCR

Mask

Local Enable

STOP

Wake up

WAIT

Wake up