Datasheet

Chapter 26 384 KByte Flash Module (S12XFTM384K2V1)
MC9S12XE-Family Reference Manual Rev. 1.25
Freescale Semiconductor 965
26.3.2.1 Flash Clock Divider Register (FCLKDIV)
The FCLKDIV register is used to control timed events in program and erase algorithms.
All bits in the FCLKDIV register are readable, bits 6–0 are write once and bit 7 is not writable.
CAUTION
The FCLKDIV register should never be written while a Flash command is
executing (CCIF=0). The FCLKDIV register is writable during the Flash
reset sequence even though CCIF is clear.
= Unimplemented or Reserved
Offset Module Base + 0x0000
76543210
R FDIVLD
FDIV[6:0]
W
Reset 00000000
= Unimplemented or Reserved
Figure 26-5. Flash Clock Divider Register (FCLKDIV)
Table 26-8. FCLKDIV Field Descriptions
Field Description
7
FDIVLD
Clock Divider Loaded
0 FCLKDIV register has not been written
1 FCLKDIV register has been written since the last reset
6–0
FDIV[6:0]
Clock Divider Bits — FDIV[6:0] must be set to effectively divide OSCCLK down to generate an internal Flash
clock, FCLK, with a target frequency of 1 MHz for use by the Flash module to control timed events during program
and erase algorithms. Table 26-9 shows recommended values for FDIV[6:0] based on OSCCLK frequency.
Please refer to Section 26.4.1, “Flash Command Operations,” for more information.
Address
& Name
76543210
Figure 26-4. FTM384K2 Register Summary (continued)