Datasheet

Chapter 24 128 KByte Flash Module (S12XFTM128K2V1)
MC9S12XE-Family Reference Manual Rev. 1.25
Freescale Semiconductor 849
24.3.2.7 Flash Status Register (FSTAT)
The FSTAT register reports the operational status of the Flash module.
CCIF, ACCERR, and FPVIOL bits are readable and writable, MGBUSY and MGSTAT bits are readable
but not writable, while remaining bits read 0 and are not writable.
3
ERSVIE1
EEE Error Type 1 Interrupt Enable — The ERSVIE1 bit controls interrupt generation when a change state error
is detected during an EEE operation.
0 ERSVIF1 interrupt disabled
1 An interrupt will be requested whenever the ERSVIF1 flag is set (see Section 24.3.2.8)
2
ERSVIE0
EEE Error Type 0 Interrupt Enable — The ERSVIE0 bit controls interrupt generation when a sector format error
is detected during an EEE operation.
0 ERSVIF0 interrupt disabled
1 An interrupt will be requested whenever the ERSVIF0 flag is set (see Section 24.3.2.8)
1
DFDIE
Double Bit Fault Detect Interrupt Enable — The DFDIE bit controls interrupt generation when a double bit fault
is detected during a Flash block read operation.
0 DFDIF interrupt disabled
1 An interrupt will be requested whenever the DFDIF flag is set (see Section 24.3.2.8)
0
SFDIE
Single Bit Fault Detect Interrupt Enable — The SFDIE bit controls interrupt generation when a single bit fault
is detected during a Flash block read operation.
0 SFDIF interrupt disabled whenever the SFDIF flag is set (see Section 24.3.2.8)
1 An interrupt will be requested whenever the SFDIF flag is set (see Section 24.3.2.8)
Offset Module Base + 0x0006
76543210
R
CCIF
0
ACCERR FPVIOL
MGBUSY RSVD MGSTAT[1:0]
W
Reset 1000000
(1)
1. Reset value can deviate from the value shown if a double bit fault is detected during the reset sequence (see Section 24.6).
0
1
= Unimplemented or Reserved
Figure 24-11. Flash Status Register (FSTAT)
Table 24-16. FERCNFG Field Descriptions (continued)
Field Description