Datasheet

Port Integration Module (S12XSPIMV1)
S12XS Family Reference Manual, Rev. 1.13
Freescale Semiconductor 105
2.3.44 Port P Data Direction Register (DDRP)
Address 0x025A Access: User read/write
1
1
Read: Anytime
Write: Anytime
76543210
R
DDRP7 DDRP6 DDRP5 DDRP4 DDRP3 DDRP2 DDRP1 DDRP0
W
Reset 00000000
Figure 2-42. Port P Data Direction Register (DDRP)
Table 2-41. DDRP Register Field Descriptions
Field Description
7
DDRP
Port P data direction—
This bit determines whether the associated pin is an input or output.
The PWM forces the I/O state to be an output for an enabled channel. If the PWM shutdown feature is enabled this
pin is forced to be an input. In this case the data direction bit will not change.
1 Associated pin configured as output
0 Associated pin configured as input
6-3
DDRP
Port P data direction—
This bit determines whether the associated pin is an input or output.
The PWM forces the I/O state to be an output for an enabled channel. In this case the data direction bit will not
change.
1 Associated pin configured as output
0 Associated pin configured as input
2,0
DDRP
Port P data direction—
This bit determines whether the associated pin is an input or output.
The PWM forces the I/O state to be an output for an enabled channel. Else the TIM forces the I/O state to be an
output for a timer port associated with an enabled output compare. Else depending on the configuration of the
enabled SCI the I/O state will be forced to be input or output. In this case the data direction bit will not change.
1 Associated pin configured as output
0 Associated pin configured as input
1
DDRP
Port P data direction—
This bit determines whether the associated pin is an input or output.
The PWM forces the I/O state to be an output for an enabled channel. Else the TIM forces the I/O state to be an
output for a timer port associated with an enabled output compare. In this case the data direction bit will not change.
1 Associated pin configured as output
0 Associated pin configured as input