Datasheet

Port Integration Module (S12XSPIMV1)
S12XS Family Reference Manual, Rev. 1.13
108 Freescale Semiconductor
2.3.49 Port P Interrupt Flag Register (PIFP)
2.3.50 Port H Data Register (PTH)
Address 0x025F Access: User read/write
1
1
Read: Anytime
Write: Anytime
76543210
R
PIFP7 PIFP6 PIFP5 PIFP4 PIFP3 PIFP2 PIFP1 PIFP0
W
Reset 00000000
Figure 2-47. Port P Interrupt Flag Register (PIFP)
Table 2-46. PIFP Register Field Descriptions
Field Description
7-0
PIFP
Port P interrupt flag—
The flag bit is set after an active edge was applied to the associated input pin. This can be a rising or a falling edge
based on the state of the polarity select register.
Writing a logic “1” to the corresponding bit field clears the flag.
1 Active edge on the associated bit has occurred (an interrupt will occur if the associated enable bit is set)
0 No active edge occurred
Address 0x0260 Access: User read/write
1
1
Read: Anytime, the data source depends on the data direction value
Write: Anytime
76543210
R
PTH7 PTH6 PTH5 PTH4 PTH3 PTH2 PTH1 PTH0
W
Reset 00000000
Figure 2-48. Port H Data Register (PTH)
Table 2-47. PTH Register Field Descriptions
Field Description
7-0
PTH
Port H general purpose input/output data—Data Register, pin interrupt input/output
The associated pin can be used as general purpose I/O. In general purpose output mode the register bit value is
driven to the pin.
If the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered
pin input state is read.
• Pin interrupts can be generated if enabled in input or output mode.