Datasheet

Port Integration Module (S12XSPIMV1)
S12XS Family Reference Manual, Rev. 1.13
112 Freescale Semiconductor
2.3.57 Port H Interrupt Flag Register (PIFH)
2.3.58 Port J Data Register (PTJ)
Address 0x0267 Access: User read/write
1
1
Read: Anytime
Write: Anytime
76543210
R
PIFH7 PIFH6 PIFH5 PIFH4 PIFH3 PIFH2 PIFH1 PIFH0
W
Reset 00000000
Figure 2-55. Port H Interrupt Flag Register (PIFH)
Table 2-54. PIFH Register Field Descriptions
Field Description
7-0
PIFH
Port H interrupt flag—
The flag bit is set after an active edge was applied to the associated input pin. This can be a rising or a falling edge
based on the state of the polarity select register.
Writing a logic “1” to the corresponding bit field clears the flag.
1 Active edge on the associated bit has occurred (an interrupt will occur if the associated enable bit is set)
0 No active edge occurred
Address 0x0268 Access: User read/write
1
1
Read: Anytime, the data source depends on the data direction value
Write: Anytime
76543210
R
PTJ7 PTJ6
0000
PTJ1 PTJ0
W
Reset 00000000
Figure 2-56. Port J Data Register (PTJ)
Table 2-55. PTJ Register Field Descriptions
Field Description
7-6, 1-0
PTJ
Port J general purpose input/output data—Data Register, pin interrupt input/output
The associated pin can be used as general purpose I/O. In general purpose output mode the register bit value is
driven to the pin.
If the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered
pin input state is read.
• Pin interrupts can be generated if enabled in input or output mode.